In the current state of GaN semiconductor devices, the standard approach toward making GaN devices such as HEMTs, on a high thermal conductivity substrate (e.g., with thermal conductivity higher than silicon carbide (SiC)) has multiple limitations. The standard approach typically starts with a Ga-polar GaN device structure grown on Si-face SiC or a Si (111) substrate that is then flip-chip surface mounted to a carrier wafer. The SiC or Si substrate and part of a GaN buffer layer is then mechanically or chemically removed and replaced by a high thermal conductivity substrate such as diamond. The standard approach typically uses surface bonding to a carrier wafer that generates surface contamination that increases the possibility of high gate leakage current and large current collapse. The standard approach typically removes a substrate and a GaN buffer to expose the highly chemically active N-face of GaN to processing, which can lead to increased buffer leakage and reduced breakdown voltage. This may, in turn, limit the operation voltage of the device and its radio-frequency (RF) performance. The standard approach may also use a considerably thick GaN buffer layer that is retained due to process control limitations, which increases the distance between a junction of the device and the high thermal conductivity substrate which compromises the thermal dissipation performance of the device. The substrate is also typically attached to the active wafer by using an interfacial adhesive material with a significantly low thermal conductivity, which increases the thermal resistance of the device significantly.